Impedance matching problems associated with use of mechanical connectors for connecting conductive traces are known. For example, the present state of the art in electrical connector technology involves the use of vias, which are holes plated with metal, to connect signal layers in multi-layer substrates. When used with high-frequency signals such as digital signals, vias contribute to problems such as impedance mismatches and cross-talk to adjacent signal layers. The extent of the problem depends upon the type of via used and related size and material characteristics.
The high frequency performance of vias depends mainly on a number of geometric features such as length of the plated-through hole, and diameter of the plated-through hole. The high frequency performance of vias further depends on the dielectric constant of the substrate dielectric layers. Other features that impact the high frequency performance of vias include the number, size, and shape of metallic pads used on the via and the number, size, and shape of the clearance holes, also called antipads, used where the plated-through hole must penetrate the metal reference planes (e.g., ground or power planes).
In view of the foregoing, it would be desirable to provide a technique for connecting signal layers in a multi-layer substrate which overcomes the above-described inadequacies and shortcomings. More particularly, it would be desirable to provide a technique for connecting signal layers and avoiding impedance mismatching in an efficient and cost effective manner.